Leading Edge Performance
* 320 MHz Internal Performance
* 3.7 ns Clock-to-Out (Pin-to-Pin)
* 0.1 ns Input Set-Up
* 0.25 ns Clock Skew
Specifications
* 12,000 to 48,000 System Gates
* Up to 249 User-Programmable I/O Pins
* Up to 1080 Flip-Flops
* 0.35? CMOS
Features(A54SX08-3FG208I datasheet and pdf download)
* 66 MHz PCI
* CPLD and FPGA Integration
* Single Chip Solution
* 100% Resource Utilization with 100% Pin Locking
* 3.3V Operation with 5.0V Input Tolerance
* Very Low Power Consumption
* Deterministic, User-Controllable Timing
* Unique In-System Diagnostic and Debug capability with Silicon Explorer II
* Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG)
* Secure Programming Technology Prevents Reverse Engineering and Design Theft
http://www.chinaicmart.com/series-A54/A54SX08-3FG208I.html
